Bit Serial Arithmetic In Dsp

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This thesis presents two prime contributions. First, digital filters for both intermediate and base band filtering for mobile communication are presented. Second, a local clock for on-chip clock generation is introduced. The intermediate frequency filter is a digital alternative to today's analog filters. It is a narrow band filter designed for the American digital mobile telephone system according to the IS-54 specification.

The digital base band filters are designed for use in some wide band research systems. Both the narrow band and the wide band filters use a wave digital lattice structure realized with bit-serial arithmetic. The clock generator is developed to increase the throughput in bit-serial designs such as the intermediate and the wide band filters above. It is a counter based clock generator i.e the counter stops a ring oscillator after the correct number of cycles has been generated. The generator is a digital alternative to analog on-chip generators as for instance PLL's. The clock is local and occupies only a small area.

Several clock generators can, therefore, be used on the same die. All work presented in this thesis is fabricated and tested in a standard 5 volt CMOS processes. The IS-54 filter is a a twelfth order narrow band filter with 20 kHz band width and a center frequency of 95 kHz. The wide-band filters are designed for two different systems; the first system is designed for 20 MHz modulated band width and the second is designed for 2 MHz modulated band width. The clock generator is used in all the filter designs and it is also tested separately in a 385 MHz clock generator. The power consumption is low.

Another more important property with respect to the power consumption is that the clock generator is suitable for low supply voltage applications. The on-chip clock generator has been tested down to 0.7 volts in a standard 5 Volts CMOS process.

All computers before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers. Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation. Real-time DSP architectures are designed to match the hardware speed. In bit-serial computation, arithmetic and logical values of all signals are.

Abstract In this paper we discuss the design and implementation of fixed-function, recursive DSP algorithms. We demonstrate by means of a wave digital lattice filter that a sampling frequency of more than 130 MHz can be achieved for a recursive algorithm by using bit-serial arithmetic. The proposed approach leads to very fast recursive algorithms with low power consumption and a minimum requirement of chip area. Further, we show that the iteration period bound by Renfors et al. Often can be lowered by applying numerical equivalence transformations to the signal-flow graph. The proposed implementation technique can easily be extended to higherorder bireciprocal and non-bireciprocal lattice filters as well as other types of DSP algorithms.